 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1041B WCFS4016C1C 256K x 16 Static RAM Features * High speed -- tAA = 15 ns * 2.0V Data Retention (400 W at 2.0V retention) * Automatic power-down when deselected * TTL-compatible inputs and outputs * Easy memory expansion with CE and OE features from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The WCFS4016C1C is available in a standard 44-pin 400-mil-wide SOJ package. Functional Description The WCFS4016C1C is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data Logic Block Diagram INPUT BUFFER Pin Configuration SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 256K x 16 ARRAY 1024 x 4096 I/O0 - I/O7 I/O8 - I/O15 COLUMN DECODER BHE WE CE OE BLE A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 ROW DECODER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 Selection Guide WCFS4016C1C 15ns Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 15 190 3 A9 A10 A 11 A 12 A 13 A 14 A 15 A 16 A17 SENSE AMPS Revised April 19, 2002 WCFS4016C1C Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature -65C to +150C Ambient Temperature with Power Applied-55C to +125C Supply Voltage on VCC to Relative GND[1]-0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1]-0.5V to VCC + 0.5V DC Input Voltage[1]-0.5V to VCC + 0.5V Current into Outputs (LOW)20 mA Operating Range Range Commercial Ambient Temperature[2] 0C to +70C VCC 5V 0.5 Electrical Characteristics Over the Operating Range Test Conditions Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current --TTL Inputs Automatic CE Power-Down Current --CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.5 -1 -1 WCFS4016C1C 15ns Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 190 40 Max. Unit V V V V A A mA mA ISB2 3 mA Page 2 of 10 WCFS4016C1C Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 R1 481 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 GND 3 ns R1 481 ALL INPUT PULSES 3.0V 90% 10% 90% 10% 3 ns Equivalent to: THEVENIN EQUIVALENT 167 1.73V OUTPUT Note: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Page 3 of 10 WCFS4016C1C Switching Characteristics[4] Over the Operating Range WCFS4016C1C 15ns Parameter READ CYCLE tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High Z[6, 7] 3 7 0 15 7 0 7 15 12 12 0 0 12 8 0 3 7 12 Z[6, 7] CE LOW to Low Z[7] CE LOW to Power-Up CE HIGH to Power-Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z [8, 9] Description Min. 1 15 Max. Unit ms ns 15 3 15 7 0 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] Byte Enable to End of Write Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Page 4 of 10 WCFS4016C1C Data Retention Characteristics Over the Operating Range Parameter VDR tCDR[3] tR[10] Description VCC for Data Retention Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 3.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V Conditions[11] Min. 2.0 0 tRC Max. Unit V ns ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1 [12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 10. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds 11. No input may exceed VCC + 0.5V 12. Device is continuously selected. OE, CE, BHE, and/or BHE = VIL.. 13. WE is HIGH for read cycle. Page 5 of 10 WCFS4016C1C Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE HIGH IMPEDANCE DATA OUT Notes: 14. Address valid prior to or coincident with CE transition LOW.. Page 6 of 10 WCFS4016C1C Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [15, 16] tWC ADDRESS CE tSA tSCE tAW tPWE WE tBW BHE, BLE tSD DATAI/O tHD tHA Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BLE BHE, tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Notes: 15. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Page 7 of 10 WCFS4016C1C Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, LOW) OE tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE H L L L L L L L OE X L L L X X X H WE X H H H L L L H BLE X L L H L L H X BHE X L H L L H L X I/O0-I/O7 High Z Data Out Data Out High Z Data In Data In High Z High Z I/O8-I/O15 High Z Data Out High Z Data Out Data In High Z Data In High Z Read All bits Read Lower bits only Read Upper bits only Write All bits Write Lower bits only Write Upper bits only Selected, Outputs Disabled Mode Power Down Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 15 Ordering Code WCFS4016C1C-JC15 Package Name J Package Type 44-Lead (400-Mil) Molded SOJ Operating Range Commercial Page 8 of 10 WCFS4016C1C Package Diagrams 44-Lead (400-Mil) Molded SOJ J Page 9 of 10 WCFS4016C1C Document Title: WCFS4016C1C 256K x 16 Static RAM REV. ** Issue Date 4/19/02 Orig. of Change XFL Description of Change New Datasheet Page 10 of 10 |
Price & Availability of WCFS4016C1C-JC15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |